1. Field of the Invention
This invention relates to a method for designing a reticle, a reticle, and a method for manufacturing a semiconductor device. More particularly, it relates to a method for designing a reticle including a step of generating a dummy pattern, a reticle, and a method for manufacturing a semiconductor device including a step of patterning a interconnection layer and a dummy layer by the use of the reticle.
2. Description of the Prior Art
Owing to the trend of data processing instruments toward functional exaltation and miniaturization, various semiconductor IC devices (LSI's) which are the components of such instruments have been naturally urged to satisfy operational enhancement and dimensional reduction as essential requirements. To satisfy these requirements, the transistor circuits to be formed on such semiconducting substrates as are made of silicon or gallium arsenide are being subjected to increasingly generous integration and miniaturization.
The fine circuits which are used for these LSI's are formed by repeating the following plurality of steps of producing thin film patterns.
To be specific, the plurality of steps comprise the steps of superposing on a substrate a thin film such as a conducting film, a semiconducting film, or an insulating film which gives rise to a circuit pattern, then applying a resist to the surface of the thin film, projecting a beam of light through the pattern of a reticle on a reduced scale onto the resist thereby effecting exposure of the resist, developing the exposed resist, curing the resist, and etching the thin film as masked with the remaining pattern of the resist.
The patterns which are formed in the reticle include various electrodes such as gates, sources, and drains, a interconnection, and contact holes in a MOS transistor, for example.
For the purpose of ensuring highly accurate formation of a pattern designed to produce a fine semiconductor integrated circuit, the exposure and the development discharge important roles among other steps mentioned above. The resist is heavily affected by a difference of level on the surface of the thin film. When the surface of a substrate to which the resist is applied happens to contain large undulations, the resist applied thereto produces fluctuations of film thickness commensurate with the undulations. As a result, the pattern is suffered to produce fluctuations of width proportionate to the undulations owing to the interference between an incident light and a reflected light. If the undulations of the surface of the substrate are still larger, the beam of light used for the exposure will be defocussed possibly to the extent of deforming the pattern.
Various methods have been proposed for overcoming the disadvantages which originate in such surface undulations as mentioned above. Among them is counted a method which, at the same time that interconnection patterns 1a through 1c are distributed as shown in FIG. 1A, comprises causing dummy patterns 2a through 2c made of the same material as the interconnection patterns 1a through 1c to be laid out between the interconnection patterns 1a through 1c (referred to hereinafter as "interconnection dummy method"). The dummy patterns 2a through 2c are separated from the interconnection patterns 1a through 1c. When interconnection layers 11a through 11c are formed by the use of a reticle on a semiconducting substrate 10, the fluctuations of film thickness of the resist which are generated depending on the presence and absence of the interconnection layers 11a through 11c are greatly alleviated.
Further, the interconnection dummy method is a highly effective means to flatten an insulating film 13 which covers the interconnection layers 11a through 11c, namely to alleviate the undulations of the surface of the substrate, as shown FIG. 1B.
JP-A-54-69393 discloses a method which comprises coating a substrate with strips of resist film thereby forming a interconnection metal film and subsequently separating the interconnection metal film by the liftoff technique into interconnection parts and non-interconnection parts as opposed to each other across a groove. Then, JP-A-57-205,886 discloses a method which, in the production of a magnetic bubble memory chip, comprises causing dummy patterns to be formed around conductor patterns intersecting transfer patterns at the same time that the conductor patterns are formed. FIG. 1B is a cross section of a semiconductor device corresponding to the cross section taken through FIG. 1A showing the reticle along the line I--I. The reference numeral 14 stands for a SOG film. Since the interconnection dummy method obviates the necessity for incorporating any special step for flattening the film surface in the process thereof as described above, it proves more advantageous than the other flattening methods in terms of throughput and cost.
The design of the dummy patterns mentioned above is attained according to the following procedure as depicted in the flow chart of FIG. 2. The states in which the interconnection patterns and the dummy patterns are formed during this procedure are shown in the plan views of FIGS. 3A through 3D. First, the interconnection patterns 1 are laid out as shown in FIG. 3A and the dummy patterns 2 are disposed as separated by a fixed distance from the corresponding interconnection patterns 1. Since the continuous areas of the dummy patterns 2 are unduly wide, they can cause a short circuit between the interconnection patterns 1. Thus, the dummy patterns 2 are divided into a plurality of portions. Specifically, a latticelike pattern 3 is superposed on the dummy patterns 2 as shown in FIG. 3B. The portions of the dummy patterns 2 which are consequently overlaid by the latticelike pattern 3 are removed to obtain a group of divided and separated dummy patterns 2d as shown in FIG. 3C. Incidentally, the width of the linear portions of the latticelike pattern 3 is equal to or larger than the width of the interconnection patterns 1.
Subsequently, the widths of the separated dummy patterns 2d are measured to find whether or not any of the patterns 2d has a width falling short of the smallest allowable width a. The term "smallest allowable width a" refers to the smallest width of the dummy patterns 2d that is allowed from the standpoint of design of pattern. If the width of the dummy patterns 2d is not more than the smallest allowable width a, the dummy layers based on the dummy patterns 2d will not be formed as expected or the dummy layers will become unduly thin and will peel off.
When none of the dummy patterns 2d is found to have a width smaller than the smallest allowable width a, the design of the dummy patterns 2d and the interconnection pattern 1 is terminated.
Conversely, when dummy patterns 2e and 2f are found to have a width smaller than the smallest allowable width a, the dummy pattern 2 which adjoined the dummy pattern 2f and which has been removed as shown in FIG. 3D is restored. Then, the pattern widths are measured again. When this measurement finds any of the dummy patterns to have a width smaller than the smallest allowable width a, that particular dummy pattern 2e is removed. This step completes the design of dummy patterns and interconnection patterns.
Incidentally, the reason for the unification of the dummy pattern 2f of a width smaller than the smallest allowable width a with the other dummy pattern 2d is that, where areas devoid of a dummy pattern are continued and interconnection layers are actually formed based on these areas, the insulating film to be formed in these areas is likely to produce depressed portions therein. Then, the reason for the removal of the dummy patterns 2e having a width smaller than the smallest allowable width a is that, when dummy layers based on the dummy patterns 2e are suffered to survive, these dummy patterns separate during the manufacture of the relevant semiconductor device and ultimately partake in causing such troubles as a short circuit in the device.
A reticle is produced on the basis of the design data of these dummy patterns and interconnection patterns configured as described above and this reticle is used for the exposure of the resist.
In the case under discussion, there arises the possibility that dummy patterns 2g which equal the square of the smallest allowable width a, namely a.times.a, will exist at the sites B and C, for example, as shown in FIG. 3D.
In this case, when the interconnection layers and the dummy layers are patterned, the dummy layers produced in the areas which coincide with the dummy patterns 2g assume the shape of a slender column and tend to peel readily from the substrate. Further, the dummy patterns in this case possibly escape being transferred and impart a missing portion to a produced pattern. Particularly when the dummy patterns escape being transferred in areas in which a plurality of dummy patterns 2g of the shape of the square of a.times.a are arranged as shown in FIG. 3D, since the formation of dummy layers is not attained and the distances between the interconnection layers in the areas are unduly large, the problem ensues that the interlayer insulating films for coating the interconnection layers in the areas will not be flattened.